1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88130cs march 2002 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. 128kx8 monolithic sram, smd 5962-89598 features access times of 15*, 17, 20, 25, 35, 45, 55ns battery back-up operation ? 2v data retention (edi88130lps) cs1#, cs2 & oe# functions for bus control inputs and outputs directly ttl compatible organized as 128kx8 commercial, industrial and military temperature ranges thru-hole and surface mount packages jedec pinout ? 32 pin sidebrazed ceramic dip, 400 mil (package 102) ? 32 pin sidebrazed ceramic dip, 600 mil (package 9) ? 32 lead ceramic soj (package 140) ? 32 pad ceramic quad lcc (package 12) ? 32 pad ceramic lcc (package 141) ? 32 lead ceramic flatpack (package 142) block diagram memory array address buffer address decoder i/o circuits a0-16 i/o0-7 we# oe# cs1# cs2 figure 1 C pin configuration single +5v (10%) supply operationthe edi88130cs is a high speed, high performance, 128kx8 bits monolithic static ram. an additional chip enable line provides system memory security during power down in non-battery backed up systems and memory banking in high speed battery backed systems where large multiple pages of memory are required. the edi88130cs has eight bi-directional input-output lines to provide simultaneous access to all bits in a word. a low power version, edi88130lps, offers a 2v data retention function for battery back-up applications. military product is available compliant to mil-prf- 38535. * 15ns access time is advanced information, contact factory for availability. 32 dip 32 soj 32 clcc 32 flatpack top view 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v cc a15 cs2# we# a13 a8 a9 a11 oe# a10 cs1# i/o7 i/o6 i/o5 i/o4 i/o3 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss 32 quad lcc top view 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 4321 32 31 30 14 15 16 17 18 19 20 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss i/o3 i/o4 i/o5 i/o6 we# a13 a8 a9 a11 oe# a10 cs1# i/o7 a12 a14 a16 nc v cc a15 cs2 pin description i/o0-7 data input/output a0-16 address inputs we# write enable cs1#, cs2 chip select oe# output enable v cc power supply v ss ground nc not connected
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88130cs march 2002 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. absolute maximum ratings parameter unit voltage on any pin relative to v ss -0.2 to 7.0 v operating temperature t a (ambient) industrial -40 to +85 c military -55 to +125 c storage temperature, ceramic -65 to +150 c power dissipation 1.7 w output current 40 ma junction temperature, t j 175 c note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this speci? cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 000v input high voltage v ih 2.2 v cc +0.5 v input low voltage v il -0.5 +0.8 v truth table oe# cs1# cs2 we# mode output power x h x x standby high z icc2, icc3 x x l x standby high z icc2, icc3 h l h h output deselect high z icc1 l l h h read data out icc1 x l h l write data in icc1 capacitance t a = +25c parameter symbol condition max unit lcc csoj,dip, flatpack address lines c i v in = vcc or vss, f = 1.0mhz 612pf data lines c o v out = vcc or vss, f = 1.0mhz 814pf these parameters are sampled, not 100% tested. 30pf 480? vcc q figure 1 figure 2 255? 5pf 480? vcc q 255? ac test conditions dc characteristics v cc = 5.0v, -55c t a +125c parameter symbol conditions min typ max units input leakage current i li v in = 0v to v cc 5a output leakage current i lo v i/o = 0v to v cc 10a operating power supply current icc1 we#, cs1# = v il , i i/o = 0ma, cs2 = v ih (15-17ns) (20ns) (25-55ns) 300 225 200 ma ma ma standby (ttl) power supply current icc2 cs1# v ih and/or cs2 v il , v in v ih or v il (17-55ns) (15ns) 25 60 ma ma full standby power supply current icc3 cs1# v cc -0.2v and/or cs2 0.2v cs (17-55ns) 3 10 ma cs (15ns) 15 ma v in v cc -0.2v or v in 0.2v lps 5 ma output low voltage v ol i ol = 8.0ma 0.4 v output high voltage v oh i oh = -4.0ma 2.4 v input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1 note: for t ehqz , t ghqz and t wlqz , cl = 5pf figure 2
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88130cs march 2002 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. parameter symbol 25ns 35ns 45ns 55ns units jedec alt. min max min max min max min max read cycle time t avav t rc 25 35 45 55 ns address access time t avqv t aa 25 35 45 55 ns chip enable access time t e1lqv t acs 25 35 45 55 ns chip enable access time t e2hqv t acs 25 35 45 55 ns chip enable to output in low z (1) t e1lqx t e2hqx t clz t clz 5 5 5 5 5 5 5 5 ns ns chip disable to output in low z (1) t e1hqz t e2lqz t chz t chz 10 10 15 15 20 20 20 20 ns ns output hold from address change t avqx t oh 0000 ns output enable to output valid t glqv t oe 10 15 20 25 ns output enable to output in low z (1) t glqx t olz 0000 ns output disable to output in high z(1) t ghqz t ohz 10 15 20 20 ns chip enable to power up (1) t e1licch t e2hicch t pu t pu 0 0 0 0 0 0 0 0 ns ns chip enable to power down (1) t e1hiccl t e2liccl t pd t pd 25 25 35 35 45 45 55 55 ns ns 1. this parameter is guaranteed by design but not tested. ac characteristics C read cycle (15 to 20ns) v cc = 5.0v, vss = 0v, -55c t a +125c parameter symbol 15ns* 17ns 20ns units jedec alt. min max min max min max read cycle time t avav t rc 15 17 20 ns address access time t avqv t aa 15 17 20 ns chip enable access time t e1lqv t e2hqv t acs t acs 15 15 17 17 20 20 ns ns chip enable to output in low z (1) t e1lqx t e2hqx t clz t clz 5 5 5 5 5 5 ns ns chip disable to output in low z (1) t e1hqz t e2lqz t chz t chz 6 6 7 7 8 8 ns ns output hold from address change t avqx t oh 333ns output enable to output valid t glqv t oe 667ns output enable to output in low z (1) t glqx t olz 000ns output disable to output in high z(1) t ghqz t ohz 568ns chip enable to power up (1) t e1licch t e2hicch t pu t pu 0 0 0 0 0 0 ns ns chip enable to power down (1) t e1hiccl t e2liccl t pd t pd 15 15 17 17 20 20 ns ns 1. this parameter is guaranteed by design but not tested. * 15ns access time is advanced information, contact factory for availability. ac characteristics C read cycle (25 to 55ns) v cc = 5.0v, vss = 0v, -55c t a +125c
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88130cs march 2002 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. ac characteristics C write cycle (15 to 20ns) v cc = 5.0v, vss = 0v, -55c t a +125c parameter symbol 15ns* 17ns 20ns units jedec alt. min max min max min max write cycle time t avav t wc 15 17 20 ns chip enable to end of write t e1lwh t e1le1h t e2hwh t e2he2l t cw t cw t cw t cw 12 12 12 12 13 13 13 13 15 15 15 15 ns ns ns ns address setup time t avwl t ave1l t ave2h t as t as t as 0 0 0 0 0 0 0 0 0 ns ns ns address valid to end of write t avwh t aw 12 13 15 ns write pulse width t wlwh t wle1h t wle2l t wp t wp t wp 12 12 12 13 13 13 15 15 15 ns ns ns write recovery time t whax t e1hax t e2lax t wr t wr t wr 0 0 0 0 0 0 0 0 0 ns ns ns data hold time t whdx t e1hdx t e2ldx t dh t dh t dh 0 0 0 0 0 0 0 0 0 ns ns ns write to output in high z (1) t wlqz t whz 070808ns data to write time t dvwh t dve1h t dve2l t dw t dw t dw 7 7 7 8 8 8 10 10 10 ns ns ns output active from end of write (1) t whqx t wlz 333ns 1. this parameter is guaranteed by design but not tested. ac characteristics C write cycle (25 to 55ns) v cc = 5.0v, vss = 0v, -55c t a +125c symbol 25ns 35ns 45ns 55ns units parameter jedec alt. min max min max min max min max write cycle time t avav t wc 25 35 45 55 ns chip enable to end of write t e1lwh t e1le1h t e2hwh t e2he2l t cw t cw t cw t cw 20 16 16 16 25 20 20 20 35 25 25 25 45 40 40 40 ns ns ns ns address setup time t avwl t ave1l t ave2h t as t as t as 0 0 0 0 0 0 0 0 0 0 0 0 ns ns ns address valid to end of write t avwh t aveh t aw t aw 20 20 25 25 35 35 45 45 ns ns write pulse width t wlwh t wle1h t wle2l t wp t wp t wp 20 20 20 30 30 30 30 30 30 35 35 35 ns ns ns write recovery time t whax t e1hax t e2lax t wr t wr t wr 0 0 0 0 0 0 5 5 5 5 5 5 ns ns ns data hold time t whdx t e1hdx t e2ldx t dh t dh t dh 0 0 0 0 0 0 0 0 0 0 0 0 ns ns ns write to output in high z (1) t wlqz t whz 010013015020 ns data to write time t dvwh t dve1h t dve2l t dw t dw t dw 15 15 15 20 20 20 20 20 20 25 25 25 ns ns ns output active from end of write (1) t whqx t wlz 3333 ns 1. this parameter is guaranteed by design but not tested.
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88130cs march 2002 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. address data i/o read cycle 1 (we# high; oe#, cs# low) t avqx t avqv t avav data 2 address 1 address 2 data 1 read cycle 2 (cs1# and/or cs2 controlled, we# high) address data i/o t avqv t e1lqv t glqv t e1lqx t glqx t avav t e1hqz t ghqz oe# icc cs1# t e1licch t e1hiccl cs2 t e2hicch t e2liccl t e2hqv t e2hqx figure 2 C timing waveform - read cycles figure 4 C write cycles 2 figure 3 C write cycle 1 address data in write cycle 1 - late write, we# controlled t avwh t wlwh t whax t e2hwh t dvwh t wlqz t whqx t avwl t whdx t avav t e1lwh cs1# data out we# cs2 address data i/o write cycle 2 - early write, cs1# controlled t e1le1h t e1hax t dve1h t e1hdx t avav cs1# we# cs2 t ave1l address data i/o write cycle 3 - early write, cs2 controlled t e2he2l t e2lax t dve2l t e2ldx t avav cs1# we# cs2 t ave2h write cycles 3
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88130cs march 2002 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. data retention characteristics (edi88130lps only) -55c t a +125c characteristic low power version only sym conditions min typ max units data retention voltage v cc v cc = 2.0v 2 C C v data retention quiescent current i ccdr cs1# v cc -0.2v and/or cs2 v ss +0.2v C 0.5 2 ma chip disable to data retention time (1) t cdr v in v cc -0.2v 0 C C ns operation recovery time (1) t r or v in 0.2v tavav* C C ns note: 1. parameter guaranteed by design, but not tested. * read cycle time figure 5 C data retention - cs1# controlled figure 6 C data retention - cs2 controlled data retention, cs2 controlled data retention mode t r vcc cs2 t cdr cs 2 0.2v v cc 4.5v 4.5v data retention, cs1# controlled data retention mode t r vcc cs1# t cdr cs1# v cc -0.2v v cc 4.5v 4.5v
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88130cs march 2002 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. package 102: 32 pin sidebrazed ceramic dip (400 mils wide) pin 1 indicator 0.020 0.016 0.200 0.125 0.100 typ 15 x 0.100 = 1.500 0.155 0.115 0.420 0.400 1.616 1.584 0.061 0.017 0.400 nom 0.060 0.040 package 12: 32 pin ceramic quad lcc all dimensions are in inches 0.050 0.040 x 45 0.560 0.458 0.442 0.540 0.120 0.060 0.055 0.045 0.028 0.022 bsc. ref. ref. 0.020 x 45 package 9: 32 pin sidebrazed ceramic dip (600 mils wide) pin 1 indicator 0.020 0.016 0.200 0.125 0.100 typ 15 x 0.100 = 1.500 0.155 0.115 1.616 1.584 0.061 0.017 0.600 nom 0.060 0.040 0.620 0.600 all dimensions are in inches all dimensions are in inches
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88130cs march 2002 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. pin 1 0.019 0.015 0.040 0.030 0.290 0.270 0.116 0.100 0.050 typ 0.420 0.400 1.00 ref 0.045 0.020 0.007 0.003 0.830 0.810 0.370 0.250 0.108 0.088 0.050 typ 0.440 0.430 0.840 0.820 0.155 0.120 0.379 ref 0.040 0.030 0.096 0.080 0.050 typ 0.405 0.395 0.840 0.820 0.028 0.022 package 142: 32 pin ceramic flatpack package 140: 32 lead ceramic soj all dimensions are in inches package 141: 32 pad ceramic lcc all dimensions are in inches all dimensions are in inches
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88130cs march 2002 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. white electronic designs sram organization, 128kx8 (130 = dual cs) technology: cs = cmos standard power (5v) lps = low power access time (ns) package type: c = 32 lead sidebrazed dip, 600 mil (package 9) f = 32 lead ceramic flatpack (package 142) l = 32 pad ceramic lcc (package 141) l32 = 32 pad ceramic quad lcc (package 12) n = 32 lead ceramic soj (package 140) t = 32 lead sidebrazed dip, 400 mil (package 102) device grade: b = mil-std-883 compliant m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c edi 8 8 130 cs x x x ordering information
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